The present invention relates to an address transition signal detecting circuit, and more particularly, to an address transition signal detecting circuit for facilitating the detection of an address transition signal in a high-density semiconductor memory device.
FIG. 1 is a block diagram of a conventional address transition signal detecting circuit. Referring to FIG. 1, the conventional address transition signal detecting circuit has a derivative signal generator 10, and an address transition pulse signal detector/generator 20.
Derivative signal generator 10 makes and generates derivative signals Ai'D, Ai' and AiD from an input address signal Ai.
Address transition pulse signal detector/generator 20 receives and combines the derivative signals, producing an address transition signal.
FIG. 2 is a circuit diagram of the conventional address transition signal detecting circuit. FIG. 3 shows waveforms of signals processed in the conventional address transition signal detecting circuit.
The operation of the conventional address transition signal detecting circuit will be discussed with reference to FIGS. 2 and 3.
When address input signal Ai is input to derivative signal generator 10, this signal is inverted and delayed in the derivative signal generator to become a signal Ai'D. Then, a signal Ai' in which the phase of address input signal Ai is inverted is obtained. In addition, a signal AiD in which address input signal Ai is delayed is obtained. These are all input to address transition pulse signal detector/generator 20.
Derivative signals Ai'D, Ai' and AiD input to address transition pulse signal detector/generator 20 are logically combined with the original address input signal, forming an address transition signal.
Referring to FIG. 3 in more detail, when the waveform of signal Ai'D in which address input signal Ai is inverted and delayed, and the waveform of signal AI' in which address input signal Ai is inverted are "1" at the same time, the waveform of address transition signal TAi becomes "0."
When inverted signal AI' and delayed signal AiD both are "0," output waveform TAi becomes "1." When the original address input signal Ai and delayed signal AiD both are "1," output waveform TAi becomes "0."
When the original address input signal Ai and inverted and delayed signal Ai'D both are "0," output waveform TAi becomes "1."
When inverted and delayed signal Ai'D and inverted signal Ai' both are "1," output waveform TAi becomes "0."
With a large number of switching devices (for instance, 14 MOSFETs) used, the conventional address transition signal detecting circuit increases the integration of semiconductor memory, raising the number of derivative signals.
Accordingly, this involves the increase of the switching device floating capacitance, causing a problem so serious as to affect the operation, especially the speed, of a semiconductor memory device.